AMD · EPYC 9005 · 2024 · SP5
The AMD EPYC 9135 is a server processor with 16 cores, released in 2024 at an MSRP of $1,214. It is part of the EPYC 9005 lineup, using the EPYC 9005 platform, and fits the SP5 socket. Internally, it is built on the "Zen 5" architecture. Thanks to AMD Simultaneous Multi-Threading (SMT), each core can handle two instruction streams simultaneously, yielding a total of 32 threads for improved parallelism. The EPYC 9135 has a base clock of 3.65 GHz and can boost up to 4.3 GHz depending on workload and thermal headroom. AMD manufactures the "Zen 5" silicon on a TSMC 3nm/4nm process node. This processor supports DDR5 memory across 12 channels, up to 6TB total, with ECC support standard for data integrity in server workloads. It supports both single-socket (1P) and dual-socket (2P) configurations, with 128 lanes of PCIe 5.0 available for storage, networking and accelerators. With a TDP of 200W, the EPYC 9135 runs hot and requires a capable cooling setup. The cache hierarchy consists of 80KB/core of L1, 1MB/core of L2, and 128MB of L3 cache — a substantial cache pool well suited to memory-bound enterprise and virtualization workloads.
Low core-count Turin SKU with high per-core clocks and full 12-channel/128-lane platform I/O — a cost-effective entry point for smaller deployments that still need Genoa/Turin-class memory bandwidth.
| Brand | AMD |
|---|---|
| Family | EPYC 9005 |
| Series | EPYC 9005 |
| Architecture | Zen 5 |
| Codename | Turin |
| Launch year | 2024 |
| Cores | 16 |
| Threads | 32 |
| Base clock | 3.65 GHz |
| Boost clock | 4.3 GHz |
| L1 cache | 80KB/core |
| L2 cache | 1MB/core |
| L3 cache | 128MB |
| TDP | 200W |
| Socket | SP5 |
| Process | TSMC 3nm/4nm |
| Memory type | DDR5 |
| Memory channels | 12 |
| Max memory | 6TB |
| PCIe lanes | 128 (PCIe 5.0) |
| ECC memory | Yes |
| Socket scalability | 1P and 2P |
| Launch MSRP | $1,214 |
| OEM / tray part number | 100-000001150 |