AMD · EPYC 9005 · 2024 · SP5
The AMD EPYC 9655 is a server processor with 96 cores, released in 2024 at an MSRP of $11,852. It is part of the EPYC 9005 lineup, using the EPYC 9005 platform, and fits the SP5 socket. Internally, it is built on the "Zen 5" architecture. Thanks to AMD Simultaneous Multi-Threading (SMT), each core can handle two instruction streams simultaneously, yielding a total of 192 threads for improved parallelism. The EPYC 9655 has a base clock of 2.6 GHz and can boost up to 4.5 GHz depending on workload and thermal headroom. AMD manufactures the "Zen 5" silicon on a TSMC 3nm/4nm process node. This processor supports DDR5 memory across 12 channels, up to 6TB total, with ECC support standard for data integrity in server workloads. It supports both single-socket (1P) and dual-socket (2P) configurations, with 128 lanes of PCIe 5.0 available for storage, networking and accelerators. With a TDP of 400W, the EPYC 9655 runs hot and requires a capable cooling setup. The cache hierarchy consists of 80KB/core of L1, 1MB/core of L2, and 384MB of L3 cache — a substantial cache pool well suited to memory-bound enterprise and virtualization workloads.
The 5th Gen Turin equivalent of the previous-gen 9654 Genoa flagship at the same 96-core count. Higher clocks, faster DDR5 support and the full 512-bit AVX-512 data path (vs Genoa's double-pumped approach) for a significant generational uplift.
| Brand | AMD |
|---|---|
| Family | EPYC 9005 |
| Series | EPYC 9005 |
| Architecture | Zen 5 |
| Codename | Turin |
| Launch year | 2024 |
| Cores | 96 |
| Threads | 192 |
| Base clock | 2.6 GHz |
| Boost clock | 4.5 GHz |
| L1 cache | 80KB/core |
| L2 cache | 1MB/core |
| L3 cache | 384MB |
| TDP | 400W |
| Socket | SP5 |
| Process | TSMC 3nm/4nm |
| Memory type | DDR5 |
| Memory channels | 12 |
| Max memory | 6TB |
| PCIe lanes | 128 (PCIe 5.0) |
| ECC memory | Yes |
| Socket scalability | 1P and 2P |
| Launch MSRP | $11,852 |
| OEM / tray part number | 100-000000674 |