AMD · EPYC 4005 · 2025 · AM5
The AMD EPYC 4585PX is a server processor with 16 cores, released in 2025 at an MSRP of $699. It is part of the EPYC 4005 lineup, using the EPYC 4005 platform, and fits the AM5 socket. Internally, it is built on the "Zen 5" architecture. Thanks to AMD Simultaneous Multi-Threading (SMT), each core can handle two instruction streams simultaneously, yielding a total of 32 threads for improved parallelism. The EPYC 4585PX has a base clock of 4.3 GHz and can boost up to 5.7 GHz depending on workload and thermal headroom. AMD manufactures the "Zen 5" silicon on a TSMC 4nm process node. This processor supports DDR5 memory across 2 channels, up to 256GB total, with ECC support standard for data integrity in server workloads. It supports single-socket (1P) configurations, with 28 lanes of PCIe 5.0 available for storage, networking and accelerators. With a TDP of 170W, the EPYC 4585PX runs hot and requires a capable cooling setup. The cache hierarchy consists of 80KB/core of L1, 1MB/core of L2, and 128MB of L3 cache — a substantial cache pool well suited to memory-bound enterprise and virtualization workloads.
The higher-cache variant of AMD's Grado desktop-platform EPYC lineup, doubling L3 cache to 128MB over the base 4565P at the same clock speeds — a meaningful difference for cache-sensitive workloads on this single-socket AM5-based platform, reflected in its higher launch price.
| Brand | AMD |
|---|---|
| Family | EPYC 4005 |
| Series | EPYC 4005 |
| Architecture | Zen 5 |
| Codename | Grado |
| Launch year | 2025 |
| Cores | 16 |
| Threads | 32 |
| Base clock | 4.3 GHz |
| Boost clock | 5.7 GHz |
| L1 cache | 80KB/core |
| L2 cache | 1MB/core |
| L3 cache | 128MB |
| TDP | 170W |
| Socket | AM5 |
| Process | TSMC 4nm |
| Memory type | DDR5 |
| Memory channels | 2 |
| Max memory | 256GB |
| PCIe lanes | 28 (PCIe 5.0) |
| ECC memory | Yes |
| Socket scalability | 1P only |
| Launch MSRP | $699 |
| Part number | 100-100001561WOF |
| OEM / tray part number | 100-000001561 |